1. Field of the Invention
The present invention relates to a floorplanning apparatus for deciding placement and routing regions of hierarchical blocks.
2. Description of Related Art
A lot of semiconductor integrated circuit devices achieve their intended functions using cells which constitute logic circuits such as AND circuits or OR circuits, flip-flops and memory circuits. These cells are subjected to placement on an integrated circuit substrate and to routing across their terminals according to a netlist.
Recently, an increasing number of cells can be mounted on a single chip thanks to improvements in the microfabrication technology of semiconductor manufacturing. Accordingly, the floorplanning, which divides the whole semiconductor integrated circuit to several hierarchical blocks and decides the placement and routing regions of the individual hierarchical blocks, is increasing its importance. Once the floorplanning has been decided, since the design of the individual hierarchical blocks can be made in parallel, the design period can be reduced considerably.
FIG. 11 is a block diagram showing a processing of a conventional floorplanning apparatus. In FIG. 11, the reference numeral 1 designates a database including a netlist (containing information about cells constituting a semiconductor integrated circuit, information indicating hierarchical blocks including the cells, and information representing interconnections between terminals of the cells). The reference numeral 2 designates a database storing library data about a chip substrate and a cell structure; and 3 designates a floorplanning apparatus. The floorplanning apparatus includes a hierarchical block selecting section 4 for accepting selecting hierarchical blocks to be subjected to placement and routing, and a placement region deciding section 5 for accepting specifying the placement and routing regions of the hierarchical blocks. The reference numeral 6 designates a memory for storing the placement and routing regions of the hierarchical blocks. The reference numeral 7 designates a placement-and-routing/circuit optimizing section for deciding optimum placement of the cells belonging to the hierarchical blocks according to the placement and routing regions of the hierarchical blocks stored in the memory 6. The reference numeral 8 designates a memory for storing placement and routing results produced by the placement-and-routing/circuit optimizing section 7.
Next, the operation of the conventional floorplanning apparatus will be described.
When deciding the placement and routing regions of the hierarchical blocks, the floorplanning apparatus 3 reads the netlist from the database 1 and the library data from the database 2, and displays them.
Referring to the netlist and library data the floorplanning apparatus 3 displays, a designer selects hierarchical blocks to be subjected to the placement and routing from among a plurality of hierarchical blocks. Specifically, operating the hierarchical block selecting section 4 of the floorplanning apparatus 3, the designer selects the hierarchical blocks to be subjected to the placement and routing.
After selecting them, the designer decides the placement and routing regions of the hierarchical blocks according to his or her expertise. Specifically, the designer designates the placement and routing regions of the hierarchical blocks by operating the placement region deciding section 5 of the floorplanning apparatus 3.
The memory 6 stores the information about the placement and routing regions of the hierarchical blocks output from the floorplanning apparatus 3. Then referring to the information stored, the placement-and-routing/circuit optimizing section 7 decides the optimum placement of the cells belonging to the hierarchical blocks and the optimum routing across the terminals of the individual cells, and stores the placement and routing results into the memory 8. Although the optimization processing of the placement and routing is carried out according to the netlist and the like stored in the databases 1 and 2, the optimization processing itself belongs to a common conventional technique.
When the memory 8 stores the placement and routing results output from the placement-and-routing/circuit optimizing section 7, the designer verifies the placement and routing results. When the placement and routing results have a problem, the designer alters the placement and routing regions of the hierarchical blocks by operating the placement region deciding section 5.
The conventional floorplanning apparatus with the foregoing configuration has a problem of taking a long time for obtaining a floor plan enabling actual placement and routing. This is because it is necessary for the designer to iterate the designation of the placement and routing regions of the hierarchical blocks, and for the placement-and-routing/circuit optimizing section 7 to iterate the optimization processing. In addition, it has another problem of requiring excellent engineers with rich experience to obtain quality floor plan.